Constrained minimization of switched capacitor converter equivalent resistance by adjusting transistor sizes and duty cycles
Mustafa Y. Yin H. Lu Y. Ruderman A.
June 2021Elsevier Ltd
Microelectronics Journal
2021#112
This paper presents a novel optimization technique for Switched Capacitor Converters (SCCs). The optimization focuses on minimizing the SCC equivalent resistance by adjusting MOSFET widths and switching duty cycles. The optimized SCC parameters are obtained from numerical optimization with constant total transistor width and switching period constraints. The transistor carrier mobilities and gate-to-source voltages are accounted during the optimization. A Fibonacci SCC with two flying capacitors is used as an example and is simulated in a 65 nm low-power process. By comparing SCC parameters before and after the optimization, we obtain certain performance improvements. Particularly, at a switching frequency of 10MHz and 50Ω load, the optimized design shows improvement in average and minimum output voltage parameters by 2.5% and 4.1%, respectively, which are caused by 20.6% reduction of the equivalent resistance. The output voltage ripple is also decreased by 22.4%. By sweeping the duty cycle and transistor widths in simulation, the optimized parameters show nearly the best performance.
Constrained optimization , Equivalent resistance , Switched Capacitor Converter (SCC) , VLSI
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Power Electronics Research Laboratory, Department of Electrical and Computer Engineering, Nazarbayev University, Nur-Sultan, 010000, Kazakhstan
State-Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, FST-ECE, University of Macau, Macao, Macao
Power Electronics Research Laboratory
State-Key Laboratory of Analog and Mixed-Signal VLSI
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