Pipelined Divider with Precomputed Multiples of Divisor

Zhexebay D. Mamanova S. Karibayev B. Skabylov A. Meirambekuly N. Ikhsan G. Namazbayev T. Tynymbayev S.
January 2026 Multidisciplinary Digital Publishing Institute (MDPI)

Electronics (Switzerland)
2026 #15 Issue 1

Division remains one of the most computationally demanding operations in digital arithmetic. Traditional algorithms, such as restoring, non-restoring, and SRT (Sweeney–Robertson–Tocher) division, are limited by sequential dependencies that reduce throughput in hardware implementations. To overcome these constraints, this work proposes a pipelined integer divider architecture that employs precomputed divisor multiples and comparator-based logic to eliminate the need for full binary adders in the quotient selection stages. The proposed design consists of a three-stage pipeline, where each stage compares the shifted partial remainder with stored multiples of the divisor (B, 2B, 3B) to generate two quotient bits per clock cycle. This approach achieves a 2× reduction in the number of computation stages compared with conventional radix-2 dividers and ensures continuous operation after an initial pipeline latency. The architecture was described in Verilog hardware description language (HDL) and implemented on a Xilinx Artix-7 (XC7A100T-1CSG324C) field-programmable gate array (FPGA) using the Xilinx ISE Design Suite 14.4. Post-synthesis simulation confirmed correct quotient and remainder generation with a maximum operating frequency of 208 MHz. The implementation occupied less than 0.3% the look-up table (LUT) resources, achieving over a twofold performance improvement compared with a non-pipelined baseline. These results demonstrate that the proposed divider provides an efficient trade-off between speed and hardware cost, making it suitable for digital signal processing and embedded computation systems.

digital arithmetic units , divisor multiples , FPGA , pipelined division , quotient digit generator , remainder generator

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Department of Electronics and Astrophysics, Al-Farabi Kazakh National University, Almaty, 050040, Kazakhstan
Department of Computer Engineering, International Information Technology University, Almaty, 050040, Kazakhstan
Institute of Telecommunications and Automation, Department of Telecommunication Engineering, Almaty University of Power Engineering and Telecommunications Named After Gumarbek Daukeyev, Almaty, 050013, Kazakhstan

Department of Electronics and Astrophysics
Department of Computer Engineering
Institute of Telecommunications and Automation

10 лет помогаем публиковать статьи Международный издатель

Книга Публикация научной статьи Волощук 2026 Book Publication of a scientific article 2026