Analysis and Synthesis of Single-Bit Adders for Multi-Bit Adders with Sequential Transfers †
Tynymbayev S. Mukasheva A. Ibragimov K. Mukhamedgali A. Sergazin G. Iliev T.
2024Multidisciplinary Digital Publishing Institute (MDPI)
Engineering Proceedings
2024#70Issue 1
This paper provides an analysis of existing single-digit binary adders from the point of view of their implementation on fans built based on metal-oxide-semiconductor field-effect transistor—MOSFETs. The synthesis of a single-digit adder with a conditional sum is carried out. The considered adders are compared in terms of speed and hardware complexity (by the number of MOSFETs). Adders perform arithmetic operations on numbers. In combination with other logical operations, adders are the core of the circuits of arithmetic logic devices that implement several different operations; they are an integral part of different processors. The most important parameters of adders are their hardware complexity and performance; therefore, many options for single-bit and multi-bit connectors with serial, parallel and combined transmissions have been developed. In the final part, a scheme of a multi-bit adder with consecutive transfers on adders with a conditional sum is given. An example of performing addition operations is given.
conditional sum adder , multi-bit adder with consecutive transfers , multiplexer , single-bit adder
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International University of Information Technology, Almaty, 050013, Kazakhstan
School of Information Technology and Engineering, Kazakh-British Technical University, Almaty, 050000, Kazakhstan
Kazakh National University named after Al-Farabi, Almaty, 050040, Kazakhstan
Academy of Logistics and Transport, Almaty, 050012, Kazakhstan
Department of Telecommunications, University of Ruse, Ruse, 7004, Bulgaria
International University of Information Technology
School of Information Technology and Engineering
Kazakh National University named after Al-Farabi
Academy of Logistics and Transport
Department of Telecommunications
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