COMPARATIVE ANALYSIS OF THE PERFORMANCE OF GENERATING CRYPTOGRAPHIC CIPHERS ON THE CPU AND FPGA

Medetov B. Serikov T. Tolegenova A. Dauren Z.
15 August 2022 Little Lion Scientific

Journal of Theoretical and Applied Information Technology
2022 #100 Issue 15 4813 - 4824 pp.

With the rapid development of technologies for the use of artificial neural networks (ANN) to solve various complex and poorly algorithmized problems, recently there have been more and more ideas to use ANN to decrypt data encrypted by cryptographic protocols such as AES. As a rule, when solving a particular problem, ANNs require large amounts of data for their training. For example, in the task of data decryption, it is necessary to have a sufficiently large array of data that make up a pair: encrypted and original information. In the case of considering block data encryption using protocols of the AES family, the sizes of input and output data for ANN can be 128 bits. Thus, to implement an ANN capable of decoding data, first of all, it is necessary to develop a generator of training data, which is an array of size Nx128, where N is the amount of data. In this paper, the possibilities of implementing a training data generator for ANN using a CPU (central processing unit) and an FPGA (field-programmable logic integrated circuit) are considered. A comparative analysis of their performance in solving this problem is also carried out. Our experimental calculations show that the FPGA based oscillator has better performance than the CPU based oscillator. Moreover, the financial costs of building an FPGA generator turn out to be noticeably lower than the financial costs required to build a computer with a CPU. Thus, in this paper, we conclude that the implementation of the training data generator on the FPGA is more profitable both in terms of performance and cost. The main result of the research is the experimental confirmation of the ability of AES-type encryption algorithms to be executed in parallel at a very high level. This statement is made on the basis of the implementation of encryption functions in the Verilog language for their execution on the FPGA, which perfectly supports parallel computing. We also inform you that we have developed a library written in the Verilog language, where all the functions for data encryption according to the AES protocols are implemented. And finally, this library was used to develop a high-speed encrypted data stream generator using AES encryption algorithms. In the future, this generator is planned to be used to generate a super-large amount of training data needed to train ANNs used to decrypt or search for vulnerabilities in encryption algorithms.

Algorithm , Artificial neural networks , Central processing unit , Encryption , Field-programmable logic integrated circuit , Flow , Programmable logic integrated circuit , Protocol , Pseudo-random number generator , Quality

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Kazakh Agrotechnical University named after S. Seifullin, Nur-Sultan, Kazakhstan
Nazarbayev University, Kabanbay Batyr Ave 53, Nur-Sultan, 010000, Kazakhstan

Kazakh Agrotechnical University named after S. Seifullin
Nazarbayev University

10 лет помогаем публиковать статьи Международный издатель

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