Prospects for the Use of Quasi-Mersen Numbers in the Design of Parallel-Serial Processors
Kadyrzhan A. Kadyrzhan K. Bakirov A. Suleimenov I.
January 2025Multidisciplinary Digital Publishing Institute (MDPI)
Applied Sciences (Switzerland)
2025#15Issue 2
It is shown that a serial-parallel processor, comparable in bit capacity to a 16-bit binary processor, can be implemented based on an algorithm built on the residue number system, a distinctive feature of which is the use of the first four quasi-Mersenne numbers, i.e., prime numbers representable as (Formula presented.). Such a set of prime numbers satisfies the criterion (Formula presented.), where (Formula presented.) is also a prime number. Fulfillment of this criterion ensures the possibility of convenient use of the considered RNS for calculating partial convolutions developed for the convenience of using convolutional neural networks. It is shown that the processor of the proposed type can be based on the use of a set of adders modulo a quasi-Mersenne number, each of which operates independently. A circuit of a modulo (Formula presented.) adder is proposed, which can be called a trigger circuit, since its peculiarity is the existence (at certain values of the summed quantities) of two stable states. The advantage of such a circuit, compared to known analogs, is the simplicity of the design. Possibilities for further development of the proposed approach related to the use of the digital logarithm operation, which allows reducing the operations of multiplication modulo (Formula presented.) to addition operations, are discussed.
computing performance , effective bit depth of adder , parallel-serial computing , quasi-Mersen numbers , residue number system (RNS) , trigger adder
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Department of Telecommunication Engineering, Institute of Communications and Space Engineering, Gumarbek Daukeev Almaty University of Power Engineering and Communications, Almaty, 050040, Kazakhstan
National Engineering Academy of the Republic of Kazakhstan, Almaty, 050010, Kazakhstan
Department of Telecommunication Engineering
National Engineering Academy of the Republic of Kazakhstan
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