Optimizing the implementation of the Saber post-quantum cryptography scheme with a hybrid architecture
Atanov S. Moldamurat K. Spada L.L. Bakyt M. Maidanov A.
February 2026Institute of Advanced Engineering and Science
Bulletin of Electrical Engineering and Informatics
2026#15Issue 1860 - 874 pp.
This paper presents a hardware–software hybrid implementation of the Saber key encapsulation mechanism (KEM) on a Terasic DE10-Nano board, which combines an ARM Cortex-A9 processor and an Intel Cyclone V field programmable gate array (FPGA). By offloading computationally intensive polynomial multiplication to a dedicated FPGA module, the hybrid design significantly reduces execution time. Experimental results show that compared to a software-only approach, the hybrid design decreases execution time by 40% for key generation, 35% for encapsulation, and 50% for decapsulation. The consistent performance gains were confirmed across the LightSaber, Saber, and FireSaber parameter sets, demonstrating that CPU-FPGA co-design offers significant efficiency improvements for post-quantum cryptography (PQC), especially on platforms with limited resources.
Field programmable gate array , Hybrid cryptomodule , Information security , Post-quantum cryptography , Saber algorithm
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Department of Computer Science, Faculty of Information Technology, L.N. Gumilyov Eurasian National University, Astana, Kazakhstan
Department of Space Technique and Technology, Faculty of Physics and Engineering, L.N. Gumilyov Eurasian National University, Astana, Kazakhstan
Centre for Cybersecurity, IoT and Cyberphysical, School of Computing, Engineering and the Built Environment, Edinburgh Napier University, Edinburgh, United Kingdom
Department of Information Security, Faculty of Information Technology, L.N. Gumilyov Eurasian National University, Astana, Kazakhstan
Department of Computer Science
Department of Space Technique and Technology
Centre for Cybersecurity
Department of Information Security
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