Design and Analysis of FPGA-based PUFs with Enhanced Performance for Hardware-oriented Security

Anandakumar N.N. Hashmi M.S. Sanadhya S.K.
13 October 2022 Association for Computing Machinery

ACM Journal on Emerging Technologies in Computing Systems
2022 #18 Issue 4

This article presents a thorough analysis of two distinct Physically Unclonable Functions (PUF), namely RO-PUF (Ring oscillator-based PUF) and RS-LPUF (RS Latch-based PUF), prototyped on FPGA. It is shown that the implemented PUFs possess significantly enhanced performance when compared to the state of the art. It is also identified that the enhancements are achieved through the incorporation of Programmable Delay Lines of FPGA Lookup Tables, the Temporal Majority Voting (TMV) scheme, and placed macro techniques for routing and placements of PUF units. The prototypes developed on Xilinx Artix-7 FPGAs are used for validation over the rated temperature range of 0-85°C with ±5% variation in the supply voltage. The proposed schemes when evaluated experimentally also achieve good uniformity, bit-aliasing, uniqueness, and reliability. Finally, it is shown that the proposed designs outperform the existing conventional PUFs in the area and speed tradeoff.

FPGA , internet of things (IoT) , PDL , PUF , RO-PUF , RS-LPUF , TMV

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Florida Institute for Cybersecurity (FICS) Research, University of Florida, Gainesville, 32603, FL, United States
School of Engineering and Digital Sciences, Nazarbayev University, 010000, Kazakhstan
School of Artificial Intelligence and Data Science, IIT-Jodhpur, Jodhpur, 342030, India

Florida Institute for Cybersecurity (FICS) Research
School of Engineering and Digital Sciences
School of Artificial Intelligence and Data Science

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